1. 개 요
○ 가산기 설계를 통한 전반적인 Modelsim, Xilinx ISE 사용법 실습
○ TEST bench, simulation 방법 이해
2. 문 제
(1) 3*8 Decoder
-Behavioral modeling
library ieee;
use ieee.std_logic_1164.all;
entity decoder is
port (x : in std_logic_vector(2 downto 0);
d : out std_logic_vector(7 downto 0));
end decoder;
architecture behavioral of decoder is
begin
process (x)
begin
case x is
when 000 =] d [= 10000000 ;
when 001 =] d [= 01000000 ;
when 010 =] d [= 00100000 ;
when 011 =] d [= 00010000 ;
when 100 =] d [= 00001000 ;
when 101 =] d [= 00000100 ;
when 110 =] d [= 00000010 ;
when others =] d [= 00000001 ;
end case;
end process;
end behavioral;
-Data flow modeling
library ieee;
use ieee.std_logic_1164.all;
entity decoder_dataflow is
port( x: in std_logic_vector(2 downto 0);
d: out std_logic_vector(7 downto 0):= 00000000 );
end decoder_dataflow;
2012.04.12
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